Pipelined enable, Output registers input registers e output buffers, Sleep control – Cypress CY7C1298H User Manual

Page 2

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CY7C1298H

Document #: 38-05665 Rev. *B

Page 2 of 16

Functional Block Diagram

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

Q1

Q0

ADSC

BW

B

BW

A

CE

1

DQ

B,

DQP

B

BYTE

WRITE REGISTER

DQ

A ,

DQP

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

OE

SENSE

AMPS

MEMORY

ARRAY

ADSP

2 A

[1:0]

MODE

CE

2

CE

3

GW

BWE

PIPELINED

ENABLE

DQ

s,

DQP

A

DQP

B

OUTPUT

REGISTERS

INPUT

REGISTERS

E

OUTPUT

BUFFERS

DQ

B ,

DQP

B

BYTE

WRITE DRIVER

DQ

A,

DQP

A

BYTE

WRITE DRIVER

SLEEP

CONTROL

ZZ

A0, A1, A

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