Contec SPI-8450-LLVA - Manual (Page 93)

CHAPTER 8 - BIOS Setup
86
SPI-8450-LLVA
8.5. Advanced Chipset Features Setup
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory resources,
such as DRAM and the external cache. It also coordinates communications between the
conventional ISA bus and the PCI bus. It must be stated that these items should never need to be
altered. The default settings have been chosen because they provide the best operating
conditions for your system. The only time you might consider making any changes would be if
you discovered that data was being lost while using your system.
Description Choice
DRAM Timing Selectable
The value in this field depends on
performance parameters of the installed
memory chips (DRAM). Do not change the
value from the factory setting unless you
install new memory that has a different
performance rating than the original DRAMs
CAS Latency Time
When synchronous DRAM is installed, the
number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset
this field from the default value specified by
the system designer.
You can select CAS latency time in HCLK of
2/2 or 3/3. The system board designer should
set the values in this field, depends on the
DRAM installed specifications of the
installed DRAM or the installed CPU.