Cypress CY7C1347G User Manual
Page 5
CY7C1347G
Document #: 38-05516 Rev. *F
Page 5 of 22
Table 1. Pin Definitions
Name
IO
Description
A
0
,A
1
,A
Input-
Synchronous
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A
[1:0]
feeds
the 2-bit counter.
BW
A,
BW
B,
BW
C,
BW
D
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when
a new external address is loaded.
CE
2
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is loaded.
CE
3
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is loaded.
OE
Input-
Asynchronous
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW,
the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE
1
is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
DQ
A,
DQ
B
DQ
C,
DQ
D
DQP
A,
DQP
B,
DQP
C,
DQP
D
IO-
Synchronous
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs
are placed in a tri-state condition.
V
DD
Power Supply
Power Supply Inputs to the Core of the Device
V
SS
Ground
Ground for the Core of the Device
V
DDQ
IO Power Supply
Power Supply for the IO circuitry
V
SSQ
IO Ground
Ground for the IO circuitry
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode pin has an internal pull up.
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the
die.