Cypress CY62167DV18 - Manual (Page 5)

CY62167DV18 MoBL
®
Document #: 38-05326 Rev. *C Page 5 of 11
Switching Characteristics (Over the Operating Range) [10]
Parameter Description
55 ns
Unit
Min Max
Read Cycle
t
RC
Read Cycle Time 55 ns
t
AA
Address to Data Valid 55 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 55 ns
t
DOE
OE LOW to Data Valid 25 ns
t
LZOE
OE LOW to LOW Z [11] 5 ns
t
HZOE
OE HIGH to High Z [11, 12] 20 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z [11] 10 ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High Z
[11, 12]
20 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power up 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power down 55 ns
t
DBE
BLE/BHE LOW to Data Valid 55 ns
t
LZBE
BLE/BHE LOW to Low Z [11] 5 ns
t
HZBE
BLE/BHE HIGH to HIGH Z [11, 12] 20 ns
Write Cycle [13]
t
WC
Write Cycle Time 55 ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End 40 ns
t
AW
Address Setup to Write End 40 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 40 ns
t
BW
BLE/BHE LOW to Write End 45 ns
t
SD
Data Setup to Write End 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High- [11, 12] 20 ns
t
LZWE
WE HIGH to Low-Z [11] 10 ns
Notes
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in “AC Test Loads and Waveforms” on page 4 .
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
12. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, BHE, BLE or both = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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