Maxim Integrated MAXQ610 - Manual (Page 79)

5-7
MAXQ610 User’s Guide
REGISTER DESCRIPTION
PI3 (0Bh, 00h) Port 3 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins .
Read/Write Access: Unrestricted read .
PI3.7 to PI3.0 Port 3 Input Register Bits 7:0. The PI3 register always reflects the logic state of its pins
when read . Note that each port pin has a weak pullup circuit when functioning as an input
and the p-channel pullup transistor is controlled by its respective PO bits . If the PO bit is set
to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off and forces the
port pin into three-state .
EIES0 (0Ch, 00h) External Interrupt Edge Select 0 Register
Initialization: EIES0 is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
EIES0.7 to EIES0.0 (IT[7:0]) Edge Select for External Interrupt Bits 7:0
ITn = 0: External Interrupt n is positive edge triggered .
ITn = 1: External Interrupt n is negative edge triggered .
EIES1 (0Dh, 00h) External Interrupt Edge Select 1 Register
Initialization: EIES1 is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
EIES1.7 to EIES1.0 (IT[15:8]) External Interrupt Edge Select Bits 15:8
ITx = 0: External interrupt x is positive edge triggered .
ITx = 1: External interrupt x is negative edge triggered .
Note: For the 32-pin package, the INT8 to INT15 functions are not present on external pins .
This register can be used as a general-purpose register as long as the user software does
not write to the EIF1 flag register since this could trigger an unplanned interrupt condition .
PD0 (10h, 00h) Port 0 Direction Register
Initialization: This register is cleared to 00h on all resets except power-fail reset . This register is unaf-
fected by power-fail reset .
Read/Write Access: Unrestricted read/write .
PD0.7 to PD0.0 Port 0 Direction Register Bits 7:0. PD0 is used to determine the direction of the port 0
function . The port pins are independently controlled by their direction bits . When a bit is set
to 1, its corresponding pin is used as an output; data in the PO register is driven on the pin .
When a bit is cleared to 0, its corresponding pin is used as an input, and allows an external
signal to drive the pin . Note that each port pins has a weak pullup circuit when functioning
as an input and the p-channel pullup transistor is controlled by its respective PO bits . If the
PO bit is set to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off
and forces the port pin into three-state .
PD1 (11h, 00h) Port 1 Direction Register
Initialization: This register is cleared to 00h on all resets except power-fail reset . This register is unaf-
fected by power-fail reset .
Read/Write Access: Unrestricted read/write .
PD1.7 to PD1.0 Port 1 Direction Register Bits 7:0. PD1 is used to determine the direction of the port 1
function . The port pins are independently controlled by their direction bit . When a bit is set
to 1, its corresponding pin is used as an output; data in the PO register is driven on the pin .
When a bit is cleared to 0, its corresponding pin is used as an input, and allows an external
signal to drive the pin . Note that each port pin has a weak pullup circuit when functioning
as an input and the p-channel pullup transistor is controlled by its respective PO bits . If the
PO bit is set to 1, the weak pullup is on, if the PO bit is cleared to 0, the weak pullup is off
and forces the port pin into three-state .