Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 57)

The first byte output by this command is the value 146 (092h), which represents the number of peripheral registers output. Table 25
lists the remaining 356 bytes output by this command.
ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG)
The MAXQ2000 provides two different interfaces for in-system programming (bootloader) operations.
• JTAG TAP interface
• Serial port 0 (UART) interface
To use either of these interfaces for in-system programming, the SPE and PSS[1:0] bits must be set through the JTAG TAP interface.
This is done while the device is held in reset, using the system-programming instruction as described in the MAXQ Family User’s Guide.
It is also possible for the MAXQ2000 to bootstrap itself into in-system programming mode by setting the proper bits in the In-Circuit
Debug Flag (ICDF) register and invoking a reset. The procedure for invoking in-system programming in this manner must be defined
by the application firmware.
Register Name: ICDF
Register Description: In-Circuit Debug Flag Register
Register Address: M1[10h]
Bit 0: (ICDF.0) Reserved
MAXQ Family User’s Guide:
MAXQ2000 Supplement
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x PO0 PO1 PO2 PO3 00 00 00 00 EIF0 EIE0
1x PI0 PI1 PI2 PI3 EIES0 00 00 00 00 00 00
2x PD0 PD1 PD2 PD3 00 00 00 00 00 00 00 00
3x 00 00 RCNT RTSS RTSH RTSL RSSA RASH RASL
4x PO4 PO5 PO6 PO7 00 00 00 00 EIF1 EIE1
5x PI4 PI5 PI6 PI7 EIES1 00 00 00 00 00 00
6x PD4 PD5 PD6 PD7 00 00 00 00 00 00 00 00
7x 00 00 00 00 00 00 00 00 00 00 00 00 SVS WKO
8x MCNT MA MB MC2 MC1 MC0 SCON0 SBUF0
9x SMD0 PR0 00 00 MC1R MC0R LCRA LCFG LCD16
Ax LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7
Bx LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15
Cx T2CNA0 T2H0 T2RH0 T2CH0 00 00 00 00 SCON1 SBUF1
Dx SMD1 PR1 00 00 00 00 T2CNB0 T2V0 T2R0 T2C0
Ex T2CFG0 00 00 00 00 OWA OWD SPICN SPICF SPICK
Fx 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10x T2CNA1 T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2
11x T2CNB1 T2V1 T2R1 T2C1 T2CNB2 T2V2 T2R2 T2C2
12x T2CFG1 T2CFG2 AP APC PSF IC IMR SC IIR CKCN WDCN 00 A[0]
13x A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8]
14x A[9] A[10] A[11] A[12] A[13] A[14] A[15] IP
15x SP + 1 IV LC[0] LC[1] Offs DPC GR BP
16x DP[0] DP[1]
Table 25. Output From DebugReadMap Command
Bit # 7 6 5 4 3 2 1 0
Name — — — — PSS1 PSS0 SPE —
Reset 0 0 0 0 0 0 0 0
Access r r r r r/w r/w r/w r
Maxim Integrated 57