Table 14-13 – Cypress enCoRe CY7C63310 User Manual
Page 39
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K
Page 39 of 83
Table 14-13. P1.3 Configuration (P13CR) [0x10] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
3.3V Drive
High Sink
Open Drain
Pull up Enable
Output Enable
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register controls the operation of the P1.3 pin. This register exists in all enCoRe II parts.
The P1.3 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled or disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the
P1 data register.
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and
Pull Up Enable control the behavior of the pin.
Table 14-14. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPI Use
Int Enable
Int Act Low
3.3V Drive
High Sink
Open Drain
Pull up Enable
Output Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
These registers control the operation of pins P1.4–P1.6, respectively. These registers exist in all enCoRe II parts.
Bit 7:
SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
The P1.4–P1.6 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by
the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable
bit and the corresponding bit in the P1 data register.
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain,
and Pull up Enable control the behavior of the pin.
Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input and output direction
of pins P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically
set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode,
pin P1.4 must be configured as an input.
Table 14-15. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
Reserved
High Sink
Open Drain
Pull up Enable
Output Enable
Read/Write
–
R/W
R/W
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
1
0
This register controls the operation of pin P1.7. This register only exists in CY7C638(1/2/3)3. The P1.7 GPIO’s threshold is
always set to TTL.
Table 14-16. P2 Configuration (P2CR) [0x15] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Int Enable
Int Act Low
TTL Thresh
Reserved
Open Drain
Pull up Enable
Output Enable
Read/Write
–
R/W
R/W
R/W
-
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register only exists in CY7C638(2/3)3. This register controls the operation of pins P2.0–P2.1.