Reference design – Connect Tech PCI-104 User Manual
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Connect Tech FreeForm/PCI-104 User Manual
Revision 0.02
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Reference Design
The FreeForm/PCI-104 ships with a pre-installed reference design that is loaded into the FPGA’s
configuration flash. This reference design demonstrates how to interface the FreeForm/PCI-104
(Virtex-5 FPGA) with the PLX PCI 9056 PCI to Local Bus Bridge, as well as the various peripherals.
The PLX 9056 provides a generic local bus that is capable of operating at up to 66MHz (this design
forwards a 50MHz clock to the PLX). The PLX bridge has been set in the C-Mode of operation. The
reference logic operates as a local bus slave, as well as a local bus master.
The reference design contains examples demonstrating:
o
Loading of PLX 9056’s registers via the local bus
o
Local bus slave transfers
o
Local bus master transfers
o
GPIO control
o
Programming the SPI Flash
o
Interfacing to the built-in Virtex-5 TEMACs
o
RS-485 serial data transfers
o
Reading/writing to the serial EEPROM
o
Reading/writing to DDR2 memory
o
Interfacing to the Virtex-5 Rocket I/O transceivers
Most of the example VHDL modules demonstrate how to interface with the various peripherals through
a register set, which is accessible by the host system over the PCI bus. A set of software applications
has been created to show how the host system can communicate with each FPGA sub-module. In most
applications, the host system will not directly control these peripherals. In a custom application, these
modules can be easily modified to interconnect with each other through the FPGA fabric.
To obtain the source code, refer to
For further details on the reference design,
refer to FreeForm/PCI-104 Reference Design Guide (CTIM-00042)