Spectrum Controls 1746sc-CTR4 - Manual (Page 40)

40
SLC 500 ™ 50 KHz Counter / Flowmeter Module
Counter Start/Stop Echo: (Status Bit 0)
This bit echo’s the setting of the Counter Enable bit set in the channels
control register. The counter enable bit allows the counter to continue to
count up or down from its present value.
Counter Input State: (Status Bit 1)
This bit shows the current value of the input state. The state of the input
will be sampled at the end of the current update cycle. For rapidly
changing counter inputs the state of this bit could be either high or low
depending on the exact time of measurement. The purpose for this bit is
to provide slow counter feedback and single count diagnosis. This bit can
also be used as a general purpose digital input line back to the PLC.
Counter Direction State: (Status Bit 2)
This bit shows the current direction of the counter. The state of the
counter direction will be sampled at the end of the current update cycle.
For rapidly changing counter inputs the state of this bit could be either
high or low depending on the exact time of measurement. The purpose
for this indicator is to provide quadrature detection feedback to aid in
system diagnosis.
Count Direction Invert Bit echo: (Status Bit 3)
This bit echo’s the state of the Count Direction bit set in the channel
configuration register. The count direction status echo’s the state of the
invert bit. It does not determine if the count is going up or down.
Count Size Selection echo (Status Bit 4)
This bit echo’s the state of the maximum counter value selected in the
configuration register. When zero the channel counter is in standard
mode and will count up to ±32K (1 word of data). When set to 1 the is
in the extended mode and will have a maximum value of 8M which is
formed using the MSW and LSW data words..
Counter Max Flag: (Status Bit 5)
The flag is set when the maximum count, based on Normal or Extended
mode, is reached. Refer to the Reset Flags, Configuration Bit 2, in the
configuration word section of this chapter for a description of this flag’s
operation.
Counter Limit Flag: (Status Bit 6)
The flag is set when the user defined count limit is reached. Refer to the
the configuration word section of this chapter for a description of this
flag’s operation.
Counter Preset Echo: (Status Bit 7)
The flag is echos the state of the preset bit on the configuration register.