Altera Early SSN Estimator - Manual (Page 10)

1–6 Chapter 1: Early SSN Estimator
Setting up the Early SSN Estimator
Early SSN Estimator User Guide for Altera Programmable Devices © November 2009 Altera Corporation
Not all banks shown in the ESE tool are available in all Altera programmable devices.
The number of I/O banks available and bank size depends on the device density.
Interpreting Early SSN Estimator Results
The ESE reports four types of results for use in guiding your early I/O design—
output low/high voltages, input threshold margins, margin okay indicators, and
maximum pin limit—as shown in
Figure 1–4 .
■ Max FPGA V
OL
—The maximum voltage output low parameter reports the highest
voltage that an FPGA pin can output when driving a low value, taking into
account SSN-induced noise.
■ Min FPGA V
OH
—The minimum voltage output high parameter reports the lowest
voltage that an FPGA pin can output when driving a high value, taking into
account SSN-induced noise.
■ V
IL
Margin/V
IH
Margin—This parameter indicates how much additional noise the
output can tolerate before violating the V
IL (DC)
voltage input low or V
IH (DC )
voltage
input high thresholds at the receiver.
■ V
IL
/V
IH
Threshold Indicator—These indicators are a quick way to verify if all the
I/O standards of a given bank have sufficient margin. If all the checks pass, the
indicators are green. If any margin is violated, the indicators are red.
■ Pin Limit—The pin limit indicates the maximum number of pins of the
corresponding I/O standard that you can use without violating noise margins,
assuming that all other I/O standard pin counts are held constant. For an I/O
standard, if the number of outputs switching is less than or equal to the pin limit
indicated, the V
IL
/V
IH
threshold indicators are green.