Altera Virtual JTAG IP Core - Manual

Virtual JTAG Megafunction (sld_virtual_jtag)
2014.03.19
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The Virtual JTAG (SLD_VIRTUAL_JTAG) megafunction is an Altera ® -provided megafunction IP core
optimized for Altera device architectures. Using megafunctions in place of coding your own logic saves
valuable design time, and offers more efficient logic synthesis and device implementation. You can scale the
megafunction's size by setting parameters.
Introduction
The Virtual JTAG megafunction provides access to the PLD source through the JTAG interface.
The Quartus ® II software or JTAG control host identifies each instance of this megafunction by a unique
index. Each megafunction instance functions in a flow that resembles the JTAG operation of a device. The
logic that uses this interface must maintain the continuity of the JTAG chain on behalf the PLD device when
this instance becomes active. The Virtual JTAG megafunction) allows you to create your own software
solution for monitoring, updating, and debugging designs through the JTAG port without using I/O pins
on the device, and is one feature in the On-Chip Debugging Tool Suite.
When you create your megafunction, you can use the MegaWizard Plug-In Manager to generate a
netlist for third-party synthesis tools. Note:
With the SLD Virtual JTAG megafunction you can build your design for efficient, fast, and productive
debugging solutions. Debugging solutions can be part of an evaluation test where you use other logic analyzers
to debug your design, or as part of a production test where you do not have a host running an embedded
logic analyzer. In addition to debugging features, you can use the Virtual JTAG megafunction to provide a
single channel or multiple serial channels through the JTAG port of the device. You can use serial channels
in applications to capture data or to force data to various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to achieve real time visibility
to the logic under test. During runtime, each tool shares the JTAG connection to transmit collected test data
to the Quartus II software for analysis. The tool set consists of a set of GUIs, megafunction intellectual
property (IP) cores, and Tcl application programming interfaces (APIs). The GUIs provide the configuration
of test signals and the visualization of data captured during debugging. The Tcl scripting interface provides
automation during runtime.
The Virtual JTAG megafunction provides you direct access to the JTAG control signals routed to the FPGA
core logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG
resource as a general-purpose serial communication interface. A complete Tcl API is available for sending
and receiving transactions into your device during runtime. Because the JTAG pins are readily accessible
during runtime, this megafunction enables an easy way to customize a JTAG scan chain internal to the
device, which you can then use to create debugging applications.
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