NEXCOM NISE 3500 - Manual (Page 66)

Copyright © 2011 NEXCOM International Co., Ltd. All Rights Reserved. 52 NISE 3500, NISE 3500M User Manual
S5 RTC Wake Settings
This section is used to configure the wake up function.
BIOS SETUP UTILITY
Version 2.00.1201. Copyright (C) 2009 American Megatrends, Inc.
Wake System with Fixed Time
Advanced
[Disabled] Enable or Disable
system wake on alarm
event. When enabled,
system will wake on the
hr::min::sec specified.
→ ←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save ESC: Exit
Wake System with Fixed Time
Enables or disables the system’s wake on alarm event. When enabled, the
system will wake up on the specified time.
CPU Configuration
This section is used to configure the CPU. It will also display detected
CPU information.
BIOS SETUP UTILITY
Version 2.00.1201. Copyright (C) 2009 American Megatrends, Inc.
Advanced
→ ←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save ESC: Exit
Enabled for Windows XP
and Linux (OS optimized
for Hyper-Threading
Technology) and Disabled
for other OS (OS not
optimized for
Hyper-Threading
Technology). When
Disabled only one thread
per enabled core is
enabled.
CPU Configuration
Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz
EMT64
Processor Speed
Processor Stepping
Microcode Revision
Processor Cores
Intel HT Technology
Hyper-Threading
Active Processor Cores
Limit CPUID Maximum
Hardware Prefetcher
Adjacent Cache Line Prefetch
Intel Virtualization Technology
Power Technology
TDC Limit
TDP Limit
Supported
2527 MHz
20652
9
2
Supported
[Enabled]
[A11]
[Disabled]
[Enabled]
[Enabled]
[Disabled]
[Energy Efficient]
0
0
Hyper-Threading
Enable this field for Windows XP and Linux which are optimized for Hyper-
Threading technology. Select disabled for other OSes not optimized for
Hyper-Threading technology. When disabled, only one thread per enabled
core is enabled.
Active Processor Cores
Used to enter the number of cores to enable in each processor package.