Aplex Technology ARCHMI-707 - Manual (Page 64)

62
Active LFP
IGD Clock Source
Fixed Graphics Memory
ALS Support
Back light Control
Back light Logic
Back light Control Lev
[Maintain Aspect Ratio]
[LVDS]
[No LVDS]
[EDP]
[External Clock]
[Internal Clock]
[128MB]
[256MB]
[Disabled]
[Enabled]
[DC]
[PWM]
[Positive]
[Negative]
[Auto]
[Disabled]
[Level 8]
[Level 1]
[Level 2]
[Level 3]
[Level 4]
[Level 5]
[Level 6]
[Level 7]
[Level 8]
[Level 9]
[Level 10]
[Level 11]
[Level 12]
[Level 13]
[Level 14]
[Level 15]