BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual
BECKHOFF Equipment
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Version 1.0
Date:
2015-01-20
Hardware Data Sheet Section III
ET1815 / ET1816
Slave Controller
IP Core for Xilinx
®
FPGAs
Release 3.00k
Section I
– Technology
(Onli
Section II
– Register Description
(Onli
Section III
– Hardware Description
Installation, Configuration, Resource
consumption, Interface specification
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Table of contents
Document Outline
- Section III – Hardware Description
- 1 Overview
- 2 Features and Registers
- 3 IP Core Installation
- 3.1 Installation on Windows PCs
- 3.2 Installation on Linux PCs
- 3.3 Files located in the lib folder
- 3.4 License File
- 3.5 IP Core Vendor ID Package
- 3.6 RSA Decryption Keys
- 3.7 Environment Variable
- 3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow
- 3.9 EtherCAT Slave Information (ESI) / XML device description for example designs
- 4 IP Core Usage
- 5 IP Core Configuration
- 6 Example Designs
- 7 FPGA Resource Consumption
- 8 IP Core Signals
- 9 Ethernet Interface
- 10 PDI Description
- 10.1 Digital I/O Interface
- 10.2 SPI Slave Interface
- 10.3 Asynchronous 8/16 bit µController Interface
- 10.4 PLB Slave Interface
- 10.5 AXI4/AXI4 LITE On-Chip Bus
- 11 Distributed Clocks SYNC/LATCH Signals
- 12 SII EEPROM Interface (I²C)
- 13 Electrical Specifications
- 14 Synthesis Constraints
- 15 Appendix