Grass Valley 8914 - Manual (Page 15)

8914 Instruction Manual 9
Functional Description
FIFO (First In First Out) delay circuit. A small delay is introduced by the
nature of the serial to parallel circuit. The output goes to the external FIFO
chip.
The FIFO circuits are used to create various amounts signal delay. In the
FPGA, a separate controller is provided for each data stream to the FIFOs.
The two controllers perform the same functions. The controller outputs the
following signals: read reset, write reset, read clock, and write clock. The
read and write clocks are the same signal, and its frequency is determined
by the width of the parallel data.
The amount of delay is determined by two 16-position rotary switches.
Depending on input signal rate, the Fine switch delays the data by 2 to 3 ms
increments. The Coarse switch delays the data by 30 to 48 ms increments.
There is a minimum circuit delay of from 1.2 to 1.799 ms (for precise adjust-
ment details, see
Adjustments, Testpoints, and Indicators on page 4 ).
FIFO Circuits
The FIFO circuits create the signal delay. The FIFO receives parallel data
from the FPGA. All clock and control signals are provided by the FPGA.
The FIFO output is sent back to the FPGA.
Line Drivers
The delayed serial data is passed to the Line Driver (transmit) circuit.
Frequency Lock LEDs
The logic to turn on and off the Signal Lock LEDs is provided by the three
Error pins from the AES/EBU receiver. A no lock error condition (Lock
LED off) indicates that the phase-lock loop in the receiver is not locked to
the incoming data stream or the input signal is not present.