Epson 8600 - Manual

EPSON ActionPC and ActionTower 8600
2/96 ActionPC and ActionTower 8600 - 1

POWER
light SPEED
light
hard disk
access light
(HDD)
drive bays
RESET
button
Slimline
computer
diskette drive POWER
button
1 2
VGA
monitor printer
(parallel
port) serial 2 serial 1 keyboard
mouse
POWER
button
RESET
button
Tower
computer
POWER light
SPEED light
hard disk
access light
(HDD)
drive bays
option
slots
VGA monitor
printer
(parallel port)
serial 2
serial 1
mouse
keyboard
power outlet
power inlet
voltage selector
switch
Computer Specifications
CPU and Memory
Controllers
64-bit CPU 586-class processor
Green PC
energy saver
Energy Star compliant, low-power, doze,
standby, and suspend modes for the CPU,
hard disk drive, and VGA display; select time-
out periods, power-saving rates, and other
options in SETUP
Memory 64-bit DRAM interface supporting 8MB RAM
standard on two 4MB SIMMs; expandable to
128MB using 4MB, 8MB, 16MB, and 32MB
SIMMs; SIMMs must be tin-plated, 72-pin,
32-bit or 36-bit, fast-page mode or EDO mode,
parity or no-parity type with access speed of
70ns or faster
ROM 128KB Phoenix ® system BIOS, video BIOS,
and SETUP code in a flash memory device on
system board
Video RAM 1MB video DRAM on system board;
expandable to 2MB using two 512KB, 40-pin,
SOJ flat pack video DRAM chips
Shadow RAM Supports shadowing of system and video
BIOS ROM into RAM; video and option ROM
shadowing selectable in SETUP
Cache 16KB of internal cache in the processor;
256KB of external cache installed on system
board with two pipelined burst SRAM chips;
internal and external cache controllable
through SETUP
Math
coprocessor
Math coprocessor built into the 586-class
processor
Clock/
calendar
Real-time clock, calendar, and CMOS RAM
socketed on system board with integrated
backup battery
PCI chipset Provides PCI caching, memory, and control
for the PCI bus and the two-channel, bus-
mastered, PCI IDE interface (described under
“Hard disk and other IDE devices” below);
integrated PCI bridge translates CPU bus
cycles to PCI bus cycles and CPU-to-PCI
memory write cycles to PCI burst cycles