Epson ARM.POWERED ARM720T - Manual (Page 220)

Index
Index-2 EPSON ARM DDI 0229B
level two 7-10
section 7-8
Device identification code 9-21,
9-22
Disabling EmbeddedICE-RT 9-11
Disabling the ETM interface 10-1
Domain 7-2
access control 7-17
faults 7-15, 7-20
E
Early termination
definition 2-17
EmbeddedICE-RT 1-3, 9-3
breakpoints
coupling with watchpoints
9-43
hardware 9-36
software 9-37
communications channel 9-14
control register 9-30
control registers 9-35
coupling breakpoints with
watchpoints 9-43
debug status register 9-26,
9-41
disabling 9-11
overview 9-10
programming 9-5, 9-7, 9-17
registers 9-33
software breakpoints 9-37
TAP controller 9-34
timing 9-44
watchpoint registers 9-33—
9-36
watchpoints 9-36
ENABLE bit 9-36
Enabling the ETM interface 10-1
ETM interface
clocks and resets 10-3
connecting 10-2
enabling and disabling 10-1
signals A-5
Exception
entering 2-10
entry and exit summary 2-11
leaving 2-11
priorities 2-14
restrictions 2-14
returning to THUMB state
from 2-11
vectors 2-13, 2-14
addresses 2-13
watchpoint 9-31
External aborts 7-21
F
FAR 7-16
Fast Context Switch Extension
2-15
Fault
address register 7-16
domain 7-20
permission 7-20
status register 7-16
translation 7-20
FCSE
relocation of low virtual ad-
dresses 2-15
Fetch
instruction 9-35
Fine page table descriptor 7-9
FIQ mode 2-4
definition 2-12
FIQ valid 8-6
FSR 7-16
G
Grant signal, AHB 6-12
H
Halt mode 9-4, 9-5
Hardware breakpoints 9-36
HBUSREQx 6-12
HGRANTx 6-12
High register
accessing from THUMB state
2-7
description 2-7
HLOCKx 6-12
HRDATA 6-11
HRESP 6-10
HWDATA 6-10
I
ID register 9-19, 9-21, 9-22
IDC
cachable bit 4-1
disable 4-2
enable 4-2
operation 4-1
read-lock-write 4-2
reset 4-2
validity 4-2
double-mapped space 4-2
software IDC flush 4-2
IDCODE instruction 9-21
Identification register,
See ID reg-
ister
Instruction
fetch 9-35
register 9-20, 9-21, 9-22, 9-23
Instruction set 1-5
ARM 1-7
Thumb 1-14
Instruction types 1-5
Interface
coprocessor 8-1
debug 9-9
JTAG 9-17
Internal coprocessor instructions
3-2
Interrupt
mask enable 9-42
Interrupts 9-33
INTEST
instruction 9-20
mode 9-24
wrapper 11-2
IRQ
valid 8-6
IRQ mode 2-4
definition 2-12
J
JTAG
BYPASS 9-21
IDCODE 9-21, 9-23
interface 9-3, 9-17
INTEST 9-20
public instructions (summary)
9-20
RESTART 9-21
SCAN_N 9-20
JTAG signals A-3
L
Large page references, translating
7-12
Level one
descriptor 7-6
descriptor, accessing 7-6
fetch 7-6
Level two
descriptor 7-10
Little endian. see memory format
Lock signal, AHB 6-12
Low registers 2-7
M
Mask enable
interrupt 9-42
Memory
access from debugging state
9-28, 9-29
Memory formats
big endian description 2-2
little endian description 2-3
Memory management unit 7-1
Miscellaneous signals A-7
MMU 7-1
enabling 3-5
enabling and disabling 7-21
faults 7-15
registers 7-3