Figure3.6 external reset circuit, External reset circuit, Input control signals—clock, reset/, ws_enable – Avago Technologies LSI53C180 User Manual
Page 46: Output control signals—bsy_led, xfer_active
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3-12
Specifications
Figure 3.6
External Reset Circuit
Table 3.13
Input Control Signals—CLOCK, RESET/, WS_ENABLE
Symbol
Parameter
Min
Max
Units
Test Conditions
V
IH
Input high voltage
2.0
V
DD
V
–
V
IL
Input low voltage
V
SS
-0.3
0.8
V
–
I
OZ
3-state leakage
−
10
10
µ
A
V
PIN
= 0 V, 5.25 V
Table 3.14
Output Control Signals
—
BSY_LED, XFER_ACTIVE
Symbol
Parameter
Min
Max
Units
Test Conditions
V
OH
Output high voltage
2.4
V
DD
V
8 mA
V
OL
Output low voltage
V
SS
0.4
V
8 mA
I
OZ
3-state leakage
−
10
10
µ
A
–
Input
3.3 V
0.1
µ
F
Reset
Pin 146
3.3 V
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