Epson S1C88650 - Manual (Page 68)

60 EPSON S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
RPTOUT2: 00FF38H•D4
RPTOUT3: 00FF39H•D4
___________ ___________
Controls the TOUT2/TOUT3 (inverted TOUT2/
TOUT3) signal output.
When "1" is written:
_________
TOUT signal output
When "0" is written: DC output
Reading:
Valid
RPTOUT2 and RPTOUT3 are the output control
___________ ___________
registers for the TOUT2 and TOUT3 signals,
respectively. When RPTOUT2 (or RPTOUT3) is set
___________ ___________
to "1", the TOUT2 (or TOUT3) signal is output from
the P17 port terminal. When "0" is set, P17 is set for
DC output.
At this time, settings of the I/O control register
IOC17 and data register P17D become invalid.
At initial reset, RPTOUT is set to "0" (DC output).
Note: If RPTOUT2 and RPTOUT3 are set to "1" at
the same time, RPTOUT3 is effective.
Furthermore, if the programmable timer is set
________
in 16-bit mode, the TOUT2 signal cannot be
output.
FOUTON: 00FF40H•D3
Controls the FOUT (f OSC1 /f OSC3 dividing clock)
signal output.
When "1" is written: FOUT signal output
When "0" is written: DC output
Reading:
Valid
FOUTON is the output control register for FOUT
signal. When "1" is set, the FOUT signal is output
from the P16 port terminal and when "0" is set, P16
is set for DC output. At this time, settings of the I/
O control register IOC16 and data register P16D
become invalid.
At initial reset, FOUTON is set to "0" (DC output).
FOUT0–FOUT2: 00FF40H•D4–D6
FOUT signal frequency is set as shown in Table
5.7.6.2.
Table 5.7.6.2 FOUT frequency settings
FOUT2 FOUT frequency
1
1
1
1
0
0
0
0
f OSC3 / 8
f OSC3 / 4
f OSC3 / 2
f OSC3 / 1
f OSC1 / 8
f OSC1 / 4
f OSC1 / 2
f OSC1 / 1
FOUT1
1
1
0
0
1
1
0
0
FOUT0
1
0
1
0
1
0
1
0
f OSC1 :
f OSC3 :
OSC1 oscillation frequency
OSC3 oscillation frequency
At initial reset, this register is set to "0" (f OSC1 /1).
5.7.7 Programming notes
(1) When changing the port terminal in which the
pull-up resistor is enabled from LOW level to
HIGH, a delay in the waveform rise time will
occur depending on the time constant of the
pull-up resistor and the load capacitance of the
terminal. It is necessary to set an appropriate
wait time for introduction of an I/O port. Make
this wait time the amount of time or more
calculated by the following expression.
Wait time = R IN x (C IN + load capacitance on the
board) x 1.6 [sec]
R IN : Pull up resistance Max. value
C IN : Terminal capacitance Max. value
(2) Since the special output signals (TOUT0–3,
_____________________________________________
TOUT2–3, and FOUT) are generated
asynchronously from the output control
registers (PTOUT0–3, RPTOUT2–3, and
FOUTON), when the signals is turned ON or
OFF by the output control register settings, a
hazard of a 1/2 cycle or less is generated.
(3) When the FOUT frequency is made "f OSC3 /n",
you must turn on the OSC3 oscillation circuit
before outputting FOUT. A time interval of
several msec to several 10 msec, from the
turning ON of the OSC3 oscillation circuit to
until the oscillation stabilizes, is necessary, due
to the oscillation element that is used.
Consequently, if an abnormality occurs as the
result of an unstable FOUT signal being output
externally, you should allow an adequate
waiting time after turning ON of the OSC3
oscillation, before turning outputting FOUT.
(The oscillation start time will vary somewhat
depending on the oscillator and on the
externally attached parts. Refer to the oscillation
start time example indicated in Chapter 8,
"ELECTRICAL CHARACTERISTICS".)
(4) The SLP instruction has executed when the
_____________________________________________
special output signals (TOUT0–3, TOUT2–3,
and FOUT) are in the enable status, an unstable
clock is output for the special output at the time
of return from the SLEEP state. Consequently,
when shifting to the SLEEP state, you should set
the special output signal to the disable status
prior to executing the SLP instruction.