ELANsat Tech OTP ROM EM78P156N - Manual (Page 25)

EM78P156N
OTP ROM
4.6 Interrupt
The EM78P156N has three falling-edge interrupts listed below:
(1) TCC overflow interrupt
(2) Port 6 Input Status Change Interrupt
(3) External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is
necessary. Each pin of Port 6 will have this feature if its status changed. Any pin configured as output or
P60 pin configured as /INT is excluded from this function. The Port 6 Input Status Changed Interrupt can
wake up the EM78P156N from the sleep mode if Port 6 is enabled prior to going into the sleep mode by
executing SLEP. When the chip wakes-up, the controller will continue to execute the succeeding
address if the global interrupt is disabled or branch to the interrupt vector 008H if the global interrupt is
enabled.
RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an
interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from
address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by
polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask
bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to
Fig. 10). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution
of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from
address 001H.
This specification is subject to change without prior notice. 25 07.29.2004 (V1.2)
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