Document Outline

• 10-Gbps Ethernet MAC MegaCore Function User Guide
  • Contents
  • 1. About This IP Core
    • 1.1. Features
    • 1.2. Release Information
    • 1.3. Device Family Support
    • 1.4. IP Core Verification
      • 1.4.1. Simulation Environment
      • 1.4.2. Compatibility Testing Environment
    • 1.5. Performance and Resource Utilization
  • 2. Getting Started with Altera IP Cores
    • 2.1. Installation and Licensing
    • 2.2. Design Flows
    • 2.3. MegaWizard Plug-In Manager Flow
      • 2.3.1. Specifying Parameters
      • 2.3.2. Simulate the IP Core
    • 2.4. Qsys System Integration Tool Design Flow
      • 2.4.1. Specify Parameters
      • 2.4.2. Complete the Qsys System
      • 2.4.3. Simulate the System
    • 2.5. 10GbE MAC Parameter Settings
  • 3. 10GbE MAC Design Examples
    • 3.1. Software and Hardware Requirements
    • 3.2. 10GbE Design Example Components
      • 3.2.0.1. Ethernet Loopback Module
      • 3.2.0.2. Base Addresses
    • 3.3. 10GbE Design Example Files
    • 3.4. Creating a New 10GbE Design
    • 3.5. 10GbE Design Example Parameter Settings
    • 3.6. 10GbE Testbenches
      • 3.6.1. 10GbE Testbench
      • 3.6.2. 10GbE Testbench Component
      • 3.6.3. 10GbE Testbench Files
      • 3.6.4. 10GbE Testbench Simulation Flow
      • 3.6.5. Simulating the 10GbE Testbench with the ModelSim Simulator
      • 3.6.6. Enabling Local Loopback
      • 3.6.7. 10GbE Simulation Timing Diagrams
    • 3.7. 10GbE Design Example Compilation and Verification in Hardware
      • 3.7.1. Compiling the 10GbE Design
      • 3.7.2. Verifying the 10GbE Design in Hardware
      • 3.7.3. Debugging
      • 3.7.4. 10GbE Design Transmit and Receive Latencies
      • 3.7.5. 10GbE Design Performance and Resource Utilization
  • 4. 10GbE MAC with IEEE1588v2 Design Example
    • 4.1. Software Requirements
    • 4.2. 10GbE with IEEE 1588v2 Design Example Components
      • 4.2.1. Base Addresses
    • 4.3. 10GbE with IEEE 1588v2 Design Example Files
    • 4.4. Creating a New 10GbE with IEEE 1588v2 Design
    • 4.5. 10GbE with IEEE 1588v2 Testbench
      • 4.5.1. 10GbE with IEEE 1588v2 Testbench
      • 4.5.2. 10GbE with IEEE 1588v2 Testbench Components
      • 4.5.3. 10GbE with IEEE 1588v2 Testbench Files
      • 4.5.4. 10GbE with IEEE 1588v2 Testbench Simulation Flow
      • 4.5.5. Simulating 10GbE with IEEE 1588v2 Testbench with ModelSim Simulator
  • 5. 1G/10GbE MAC Design Example
    • 5.1. Software and Hardware Requirements
    • 5.2. 1G/10GbE Design Example Components
      • 5.2.1. Reconfiguration Bundle Parameters
      • 5.2.2. Base Addresses
    • 5.3. 1G/10GbE Design Example Files
    • 5.4. Creating a New 1G/10GbE Design
    • 5.5. 1G/10GbE Testbench
      • 5.5.1. 1G/10GbE Testbench
      • 5.5.2. 1G/10GbE Testbench Components
      • 5.5.3. 1G/10GbE Testbench Files
      • 5.5.4. 1G/10GbE Testbench Simulation Flow
        • 5.5.4.1. 1G/10Gb Ethernet Mode
        • 5.5.4.2. Backplane-KR Mode
      • 5.5.5. Simulating the 1G/10GbE Testbench with the ModelSim Simulator
      • 5.5.6. 1G/10GbE Simulation Timing Diagrams
    • 5.6. 1G/10GbE Design Example Compilation
      • 5.6.1. Compiling the 1G/10GbE Design
      • 5.6.2. 1G/10GbE Design Performance and Resource Utilization
  • 6. 10M-10GbE MAC with IEEE 1588v2 Design Example
    • 6.1. Software and Hardware Requirements
    • 6.2. 10M-10GbE MAC with IEEE 1588v2 Design Example Components
      • 6.2.1. Base Addresses
    • 6.3. 10M-10GbE MAC with IEEE 1588v2 Design Example Files
    • 6.4. Creating a New 10M-10GbE MAC with IEEE 1588v2 Design
    • 6.5. 10M-10GbE with IEEE 1588v2 Testbench
      • 6.5.1. 10M-10GbE with IEEE 1588v2 Testbench
      • 6.5.2. 10M-10GbE with IEEE 1588v2 Testbench Components
      • 6.5.3. 10M-10GbE MAC with IEEE 1588v2 Testbench Files
      • 6.5.4. 10M-10GbE MAC with IEEE 1588v2 Testbench Simulation Flow
      • 6.5.5. Simulating 10M-10GbE MAC with IEEE 1588v2 Testbench with ModelSim Simulator
  • 7. Functional Description
    • 7.1. Architecture
    • 7.2. Interfaces
      • 7.2.1. Avalon-ST Interface
      • 7.2.2. SDR XGMII
      • 7.2.3. GMII
      • 7.2.4. MII
      • 7.2.5. Avalon-MM Control and Status Register Interface
    • 7.3. Frame Types
    • 7.4. Transmit Datapath
      • 7.4.1. Frame Payload Padding
      • 7.4.2. Address Insertion
      • 7.4.3. Frame Check Sequence (CRC-32) Insertion
      • 7.4.4. XGMII Encapsulation
      • 7.4.5. Inter-Packet Gap Generation and Insertion
      • 7.4.6. SDR XGMII Transmission
    • 7.5. Receive Datapath
      • 7.5.1. Minimum Inter-Packet Gap
      • 7.5.2. XGMII Decapsulation
      • 7.5.3. Frame Check Sequence (CRC-32) Checking
      • 7.5.4. Address Checking
      • 7.5.5. Frame Type Checking
      • 7.5.6. Length Checking
      • 7.5.7. CRC-32 and Pad Removal
      • 7.5.8. Overflow Handling
    • 7.6. Transmit and Receive Latencies
    • 7.7. Congestion and Flow Control
      • 7.7.1. IEEE 802.3 Flow Control
        • 7.7.1.1. Pause Frame Reception
        • 7.7.1.2. Pause Frame Transmission
      • 7.7.2. Priority-Based Flow Control
        • 7.7.2.1. PFC Frame Reception
        • 7.7.2.2. PFC Frame Transmission
    • 7.8. Error Handling (Link Fault)
    • 7.9. IEEE 1588v2
      • 7.9.1. Architecture
      • 7.9.2. Transmit Datapath
      • 7.9.3. Receive Datapath
      • 7.9.4. Frame Format
        • 7.9.4.1. PTP Packet in IEEE 802.3
        • 7.9.4.2. PTP Packet over UDP/IPv4
        • 7.9.4.3. PTP Packet over UDP/IPv6
  • 8. Registers
    • 8.1. MAC Registers
      • 8.1.1. Rx_frame_control Register
      • 8.1.2. Rx_pfc_control Register
    • 8.2. MAC Registers for IEEE 1588v2 Feature
      • 8.2.1. Configuring PMA Analog and Digital Delay
    • 8.3. Register Initialization
  • 9. Interface Signals
    • 9.0.1. Clock and Reset Signals
    • 9.0.2. Avalon-ST Transmit and Receive Interface Signals
      • 9.0.2.1. Timing Diagrams—Avalon-ST Transmit Interface
      • 9.0.2.2. Timing Diagrams—Avalon-ST Receive Interface
    • 9.0.3. SDR XGMII
      • 9.0.3.1. Timing Diagrams—SDR XGMII
    • 9.0.4. GMII Signals
    • 9.0.5. MII Signals
    • 9.0.6. Avalon-MM Programming Interface Signals
    • 9.0.7. Avalon-ST Status and Pause Interface Signals
    • 9.0.8. 10M-10GbE MAC Speed Control Signal
    • 9.0.9. IEEE 1588v2 Interface Signals
      • 9.0.9.1. IEEE 1588v2 Timestamp Interface Signals
      • 9.0.9.2. ToD Clock Interface Signals
      • 9.0.9.3. Path Delay Interface Signals
      • 9.0.9.4. Timing Diagrams—IEEE 1588v2 Timestamp
  • 10. Design Considerations
    • 10.1. SDR XGMII to DDR XGMII Conversion
      • 10.1.1. ALTDDIO_IN Megafunction Configuration
      • 10.1.2. ALTDDIO_OUT Megafunction Configuration
    • 10.2. 10GbE MAC and PHY Connection with XGMII
    • 10.3. Sharing TX and RX Clocks for Multi-Port System Design
    • 10.4. Sharing Reference Clocks for Multi-Port System Design
  • A. Frame Format
    • A.1. Ethernet Frame
    • A.2. VLAN and Stacked VLAN Tagged MAC Frame
    • A.3. Pause Frame
    • A.4. Priority-Based Flow Control Frame
  • B. Time-of-Day (ToD) Clock
    • B.1. Features
    • B.2. Device Family Support
    • B.3. Performance and Resource Utilization
    • B.4. Parameter Setting
    • B.5. ToD Clock Interface Signals
      • B.5.1. Avalon-MM Control Interface Signal
      • B.5.2. Avalon-ST Transmit Interface Signal
    • B.6. ToD Clock Configuration Register Space
      • B.6.1. Adjusting ToD’s Drift
  • C. Packet Classifier
    • C.1. Block Diagram
    • C.2. Packet Classifier Signals
      • C.2.1. Common Clock and Reset Signals
      • C.2.2. Avalon-ST Interface Signals
      • C.2.3. Ingress Control Signals
      • C.2.4. Control Insert Signals
      • C.2.5. Timestamp Field Location Signals
  • D. ToD Synchronizer
    • D.1. Device Family Support
    • D.2. Block Diagram
    • D.3. ToD Synchronizer Parameter Settings
    • D.4. ToD Synchronizer Signals
      • D.4.1. Common Clock and Reset Signals
      • D.4.2. Interface Signals
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions