Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
User guide 10-gbps ethernet mac megacore function
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Table of contents
Document Outline
- 10-Gbps Ethernet MAC MegaCore Function User Guide
- Contents
- 1. About This IP Core
- 2. Getting Started with Altera IP Cores
- 3. 10GbE MAC Design Examples
- 4. 10GbE MAC with IEEE1588v2 Design Example
- 5. 1G/10GbE MAC Design Example
- 5.1. Software and Hardware Requirements
- 5.2. 1G/10GbE Design Example Components
- 5.3. 1G/10GbE Design Example Files
- 5.4. Creating a New 1G/10GbE Design
- 5.5. 1G/10GbE Testbench
- 5.6. 1G/10GbE Design Example Compilation
- 6. 10M-10GbE MAC with IEEE 1588v2 Design Example
- 7. Functional Description
- 8. Registers
- 9. Interface Signals
- 9.0.1. Clock and Reset Signals
- 9.0.2. Avalon-ST Transmit and Receive Interface Signals
- 9.0.3. SDR XGMII
- 9.0.4. GMII Signals
- 9.0.5. MII Signals
- 9.0.6. Avalon-MM Programming Interface Signals
- 9.0.7. Avalon-ST Status and Pause Interface Signals
- 9.0.8. 10M-10GbE MAC Speed Control Signal
- 9.0.9. IEEE 1588v2 Interface Signals
- 10. Design Considerations
- A. Frame Format
- B. Time-of-Day (ToD) Clock
- C. Packet Classifier
- D. ToD Synchronizer
- Additional Information