Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 144)

Chapter 9: Interface Signals 9–25
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
9.0.9.2. ToD Clock Interface Signals
Table 9–13 describes the ToD clock interface signals for the IEEE 1588v2 feature.
9.0.9.3. Path Delay Interface Signals
Table 9–14 describes the path delay interface signals for the IEEE 1588v2 feature.
Table 9–13. ToD Clock Interface Signals
Signal Direction Width Description
tx_time_of_day_96b_10g_data
(in 10 Gbps mode)
tx_time_of_day_96b_1g_data
(in 1 Gbps, 10 Mbps, and 100 Mbps mode)
Input 96
Use this bus to carry the time-of-day from external
ToD module to 96-bit MAC TX clock.
Consists of 48-bit seconds field, 32-bit
nanoseconds field, and 16-bit fractional
nanoseconds field
rx_time_of_day_96b_10g_data
(in 10 Gbps mode)
rx_time_of_day_96b_1g_data
(in 1 Gbps, 10 Mbps, and 100 Mbps mode)
Input 96
Use this bus to carry the time-of-day from external
ToD module to 96-bit MAC RX clock.
Consists of 48-bit seconds field, 32-bit
nanoseconds field, and 16-bit fractional
nanoseconds field
tx_time_of_day_64b_10g_data
(for 10 Gbps mode)
tx_time_of_day_64b_1g_data
(in 1 Gbps, 10 Mbps, and 100 Mbps mode)
Input 64
Use this bus to carry the time-of-day from ToD
clock to 64-bit MAC TX clock.
Consists of 48-bit nanoseconds field and 16-bit
fractional nanoseconds field
rx_time_of_day_64b_10g_data
(in 10 Gbps mode)
rx_time_of_day_64b_1g_data
(in 1 Gbps, 10 Mbps, and 100 Mbps mode)
Input 64
Use this bus to carry the time-of-day from external
ToD module to 64-bit MAC RX clock.
Consists of 48-bit nanoseconds field and 16-bit
fractional nanoseconds field
Table 9–14. Path Delay Interface Signals
Signal Direction Width Description
tx_path_delay_10g_data
(in 10 Gbps mode)
Input 16
Connect this bus to the Altera PHY IP. This bus
carries the path delay on the transmit datapath.
The delay is measured between the physical
network and XGMII SDR. The delay is used to
adjust the egress timestamp.
Consists of:
■ Bits 0 to 9: Fractional number of clock cycle
■ Bits 10 to 15: Number of clock cycle
tx_path_delay_1g_data
(in 1 Gbps, 10 Mbps, and 100 Mbps mode)
Input 22
Connect this bus to the Altera PHY IP. This bus
carries the path delay on the transmit datapath.
The delay is measured between the physical
network, and GMII and MII. The delay is used to
adjust the egress timestamp.
Consists of:
■ Bits 0 to 9: Fractional number of clock cycle
■ Bits 10 to 21: Number of clock cycle