Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 139)

9–20 Chapter 9: Interface Signals
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
9.0.8. 10M-10GbE MAC Speed Control Signal
The speed_sel signal is the input status signal from the PHY that determines the
speed for the MAC. The signal indicates the following speeds:
■ 0 = 10 Gbps
■ 1 = 1 Gps
■ 2 = 100 Mbps
■ 3 = 10 Mbps
9.0.9. IEEE 1588v2 Interface Signals
9.0.9.1. IEEE 1588v2 Timestamp Interface Signals
Table 9–10 describes the RX ingress timestamp interface signals for the IEEE 1588v2
feature.
avalon_st_rx_pause_length_data[] Output 16
This signal is present only in the MAX RX only
variation.
Specifies the pause duration when a pause frame is
sent to the TX path. The pause length is in unit of pause
quanta, where 1 pause length = 512 bits time.
avalon_st_rx_pause_length_valid Output 1
This signal is present only in the MAX RX only
variation.
When asserted, this signal qualifies the data on the
avalon_st_rx_pause_length_data
bus.
Note to Table 9–9 :
(1) The signal is present only when you turn on the Priority-based flow control (PFC) parameter.
Table 9–9. Avalon-ST Flow Control Signals (Part 3 of 3)
Signal Direction Width Description
Table 9–10. IEEE 1588v2 RX Ingress Timestamp Interface Signals (Part 1 of 2)
Signal Direction Width Description
rx_ingress_timestamp_96b_data Output 96
Carries the ingress timestamp on the receive
datapath. Consists of 48-bit seconds field, 32-bit
nanoseconds field, and 16-bit fractional
nanoseconds field.
The MAC presents the timestamp for all receive
frames and asserts this signal in the same clock
cycle it asserts
rx_ingress_timestamp_96b_valid
.
rx_ingress_timestamp_96b_valid Output 1
When asserted, this signal indicates that
rx_ingress_timestamp_96b_data
contains
valid timestamp.
For all receive frame, the MAC asserts this signal
in the same clock cycle it receives the start of
packet (avalon_st_rx_startofpacket is
asserted).