Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 17)

Chapter 2: Getting Started with Altera IP Cores 2–5
Qsys System Integration Tool Design Flow
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
4. Specify the required parameters in the Qsys tool. For detailed explanations of
these parameters, refer to “10GbE MAC Parameter Settings” on page 2–6 .
5. Click Finish to complete the IP core instance and add it to the system.
2.4.2. Complete the Qsys System
To complete the Qsys system, follow these steps:
1. Add and parameterize any additional components.
2. Connect the components using the Connections panel on the System Contents
tab.
3. In the Export As column, enter the name of any connections that should be a
top-level Qsys system port.
4. If you intend to simulate your Qsys system, on the Generation tab, turn on one or
more options under Simulation to generate desired simulation files.
5. If you want to generate synthesis RTL files, turn on Create HDL design files for
synthesis .
6. Click Generate to generate the system. Qsys generates the system and produces
the <system name>.qip file that contains the assignments and information required
to process the IP core or system in the Quartus II Compiler.
7. In the Quartus II software, click Add/Remove Files in Project on the Project menu
and add the .qip file to the project.
8. Compile your design in the Quartus II software.
2.4.3. Simulate the System
During system generation, Qsys generates a functional simulation model which you
can use to simulate your system easily in any Altera-supported simulation tool.
f For information about the latest Altera-supported simulation tools, refer to the
Quartus II Software Release Notes .
f
For general information about simulating Altera IP cores, refer to Simulating Altera
Designs in volume 3 of the Quartus II Handbook.
f
For information about simulating Qsys systems, refer to the System Design with Qsys
section in volume 1 of the Quartus II Handbook.