Altera Arria V GZ Avalon-ST User Manual
Arria v gz avalon-st interface for pcie solutions, User guide
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Table of contents
Document Outline
- Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Arria V GZ Hard IP for PCI Express
- Qsys Design Flow
- Generating the Testbench
- Simulating the Example Design
- Generating Quartus II Synthesis Files
- Understanding the Files Generated
- Understanding Simulation Log File Generation
- Understanding Physical Placement of the PCIe IP Core
- Compiling the Design in the Qsys Design Flow
- Modifying the Example Design
- Using the IP Catalog To Generate Your Arria V GZ Hard IP for PCI Express as a Separate Component
- Qsys Design Flow
- 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
- 4. Parameter Settings
- 5. Interfaces and Signal Descriptions
- Avalon‑ST RX Interface
- Avalon‑ST RX Component Specific Signals
- Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
- Tradeoffs to Consider when Enabling Multiple Packets per Cycle
- Avalon-ST TX Interface
- Clock Signals
- Reset, Status, and Link Training Signals
- ECRC Forwarding
- Error Signals
- Interrupts for Endpoints
- Interrupts for Root Ports
- Completion Side Band Signals
- Parity Signals
- LMI Signals
- Transaction Layer Configuration Space Signals
- Hard IP Reconfiguration Interface
- Power Management Signals
- Physical Layer Interface Signals
- Avalon‑ST RX Interface
- 6. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- Type 1 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 7. Reset and Clocks
- 8. Interrupts
- 9. Error Handling
- 10. IP Core Architecture
- 11. Transaction Layer Protocol (TLP) Details
- 12. Throughput Optimization
- 13. Design Implementation
- 14. Optional Features
- 15. Hard IP Reconfiguration
- 16. Transceiver PHY IP Reconfiguration
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- DMA Write Cycles
- DMA Read Cycles
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- ebfm_barwr Procedure
- ebfm_barwr_imm Procedure
- ebfm_barrd_wait Procedure
- ebfm_barrd_nowt Procedure
- ebfm_cfgwr_imm_wait Procedure
- ebfm_cfgwr_imm_nowt Procedure
- ebfm_cfgrd_wait Procedure
- ebfm_cfgrd_nowt Procedure
- BFM Configuration Procedures
- BFM Shared Memory Access Procedures
- BFM Log and Message Procedures
- Verilog HDL Formatting Functions
- Procedures and Functions Specific to the Chaining DMA Design Example
- Debugging Simulations
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Lane Initialization and Reversal
- C. Additional Information