Altera Arria V GZ Avalon-ST - Manual (Page 283)

Date Version Changes Made
2013.05.06 13.0 • Added support for Configuration Space Bypass Mode, allowing
you to design a custom Configuration Space and support multiple
functions
• Added preliminary support for a Avalon-MM 256-Bit Hard IP for
PCI Express that is capable of running at the Gen3 ×8 data rate.
This new IP Core. Refer to the Avalon-MM 256-Bit Hard IP for
PCI Express User Guide for more information.
• Added Gen3 PIPE simulation support.
• Added support for 64-bit address in the Avalon-MM Hard IP for
PCI Express IP Core, making address translation unnecessary
• Added instructions for running the Single Dword variant.
• Timing models are now final.
• Updated the definition of
refclk
to include constraints when CvP
is enabled.
• Added section covering clock connectivity for reconfiguration
when CvP is enabled.
• Corrected access field in Root Port TLP Data registers.
• Added Getting Started chapter for Configuration Space Bypass
mode.
• Added signal and register descriptions for the Gen3 PIPE
simulation.
• Added 64-bit addressing for the Avalon-MM IP Cores for PCI
Express.
• Changed descriptions of
rx_st_err[1:0]
,
tx_st_err[1:0]
,
rx_
st_valid[1:0]
, and
tx_st_valid[1:0]
buses. Bit 1 is not used.
• Corrected definitions of
RP_RXCPL_STATUS.SOP
and
RP_RXCPL_
STATUS.
EOP bits.
SOP
is 0x2010, bit[0] and
EOP
is 0x2010, bit[1].
• Improved explanation of relaxed ordering of transactions and
provided examples.
• Revised discussion of Transceiver Reconfiguration Controller IP
Core. Offset cancellation is not required for Gen1 or Gen2
operation.
2011.07.30 11.01 Corrected typographical errors.
2011.05.06 11.0 First release.
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2014.12.15
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