Altera Arria V GZ Avalon-ST - Manual (Page 270)

Disable the Scrambler for Gen1 and Gen2 Simulations
The encoding scheme implemented by the scrambler applies a binary polynomial to the data stream to
ensure enough data transitions between 0 and 1 to prevent clock drift. The data is decoded at the other
end of the link by running the inverse polynomial.
Complete the following steps to disable the scrambler:
1. Open
<work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altpcie_tbed_<dev>_hwtcl.v .
2. Search for the string,
test_in
.
3. To disable the scrambler, set
test_in[2] = 1
.
4. Save
altpcie_tbed_sv_hwtcl.v
.
Changing between the Hard and Soft Reset Controller
The Hard IP for PCI Express includes both hard and soft reset control logic. By default, Gen1 devices use
the Hard Reset Controller. Gen2 and Gen3 devices use the soft reset controller. For variants that use the
hard reset controller, changing to the soft reset controller provides greater visibility.
Complete the following steps to change to the soft reset controller:
1. Open
<work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/<variant>.v .
2. Search for the string,
hip_hard_reset_hwtcl
.
3. If
hip_hard_reset_hwtcl = 1
, the hard reset controller is active. Set
hip_hard_reset_hwtcl = 0
to
change to the soft reset controller.
4. Save
variant.v
.
Use Third-Party PCIe Analyzer
A third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic,
saving you the trouble of translating the symbols yourself. A third-party logic analyzer can show the
two-way traffic at different levels for different requirements. For high-level diagnostics, the analyzer
shows the LTSSM flows for devices on both side of the link side-by-side. This display can help you see the
link training handshake behavior and identify where the traffic gets stuck. A traffic analyzer can display
the contents of packets so that you can verify the contents. For complete details, refer to the third-party
documentation.
BIOS Enumeration Issues
Both FPGA programming (configuration) and the initialization of a PCIe link require time. Potentially,
an Altera FPGA including a Hard IP block for PCI Express may not be ready when the OS/BIOS begins
enumeration of the device tree. If the FPGA is not fully programmed when the OS/BIOS begins its
enumeration, the OS does not include the Hard IP for PCI Express in its device map.
You can use either of the following two methods to eliminate this issue:
• You can perform a soft reset of the system to retain the FPGA programming while forcing the OS/
BIOS to repeat its enumeration.
• You can use CvP to program the device.
18-8 Disable the Scrambler for Gen1 and Gen2 Simulations
UG-01127_avst
2014.12.15
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