Altera Arria V GZ Avalon-ST User Manual
Page 117
Table 5-24: PIPE Interface Signals
Signal
Direction
Description
txdata0[7:0]
Output
Transmit data <n>. This bus transmits data on lane <n>.
txdatak0
Output
Transmit data control <n>. This signal serves as the control bit
for
txdata
<n>.
txblkst0
Output
For Gen3 operation, indicates the start of a block in the transmit
direction.
txdataskip0
Output
For Gen3 operation. Allows the MAC to instruct the TX interface
to ignore the TX data interface for one clock cycle. The following
encodings are defined:
• 1’b0: TX data is invalid
• 1’b1: TX data is valid
tx_deemph0
Output
Transmit de-emphasis selection. The Arria V GZ Hard IP for
PCI Express sets the value for this signal based on the indication
received from the other end of the link during the Training
Sequences (TS). You do not need to change this value.
rxdata0[7:0]
(2)
Input
Receive data <n>. This bus receives data on lane <n>.
rxdatak0
(2)
Input
Receive data <n>. This bus receives data on lane <n>. Bit 0
corresponds to the lowest-order byte of
rxdata
, and so on. A
value of 0 indicates a data byte. A value of 1 indicates a control
byte. For Gen1 and Gen2 only.
rxblkst0
Input
For Gen3 operation, indicates the start of a block in the receive
direction.
txdetectrx0
Output
Transmit detect receive <n>. This signal tells the PHY layer to
start a receive detection operation or to begin loopback.
txelecidle
Output
Transmit electrical idle <n>. This signal forces the TX output to
electrical idle.
txcompl0
Output
Transmit compliance <n>. This signal forces the running
disparity to negative in Compliance Mode (negative COM
character).
rxpolarity0
Output
Receive polarity <n>. This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
UG-01127_avst
2014.12.15
PIPE Interface Signals
5-65
Interfaces and Signal Descriptions
Altera Corporation