Altera Arria V GZ Avalon-ST User Manual
Page 35
The timing diagram illustrates the following sequence of events:
1. The Application Layer indicates it is ready to receive requests by asserting
RxSTReady_o
. The RX
Avalon-ST interface initiates a Memory Write to Function 1, asserting its
RxStSop_i
and
RxStValid_i
signals.
2. At the falling edge of
RxStSop_i
,
RxmFunc1Sel_o
is asserted and the write data is driven on
RxmWrite-
Data_0_o[31:0]
. The Memory Write to Function 1 completes when the data is written.
3. The Application Layer indicates it is ready to receive requests by asserting
RxSTReady_o
. The RX
Avalon-ST interface initiates a Memory Read to Function 1, asserting its
RxStSop_i
and
RxStValid_i
signals.
4. After the falling edge of
RxStSop_i
, the RX Avalon-MM master interface asserts
RxmRead_0_o
to
Function 1.
5. At the falling edge of
RxmRead_0_o
, Function 1 asserts
RxmReadDataValid_0
and drives the data on
RxmReadData_0_i[
31:0]
.
6. The host receives the completion data when
TxStValid_o
,
TxStSop_o
, and
TxStEop_o
are asserted.
Partial Transcript for Configuration Space Bypass Simulation
The driver performs the following transactions with status of the transactions displayed in the ModelSim
simulation message window:
• Various configuration reads and writes to the Avalon-MM Arria V GZ Hard IP for PCI Express in
your system after the link is initialized
• Register writes, reads and compares to both functions
• Burst memory writes, reads, and compares to both functions
The following example shows the transcript from a successful simulation run.
Example 3-1: Transcript from ModelSim Simulation of Gen1 x4 Endpoint
# INFO: 464 ns Completed initial configuration of Root Port.
# 495000: INFO: top_tb.top_inst_reset_bfm.reset_deassert: Reset deasserted
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17257 ns RP LTSSM State: DETECT.QUIET
# INFO: 20473 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 21193 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 29909 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 30949 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 33957 ns EP LTSSM State: POLLING.CONFIG
# INFO: 34025 ns RP LTSSM State: DETECT.QUIET
# INFO: 37241 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 37961 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 39945 ns RP LTSSM State: POLLING.CONFIG
# INFO: 41033 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 41445 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 41765 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 42057 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 42249 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 42789 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 43033 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 43109 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 43225 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 43685 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 44953 ns RP LTSSM State:CONFIG.IDLE
# INFO: 47941 ns EP LTSSM State: CONFIG.IDLE
UG-01127_avst
2014.08.18
Partial Transcript for Configuration Space Bypass Simulation
3-11
Getting Started with the Configuration Space Bypass Mode Qsys Example Design
Altera Corporation