Altera Arria V GZ Avalon-ST - Manual (Page 165)

Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge
handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐
ration Space and is programmable using Configuration Space accesses.
• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In
contrast to the MSI capability structure, which contains all of the control and status information for
the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X
PBA structure which are stored in memory.
• Legacy interrupts—The
app_int_sts
port controls legacy interrupt generation. When
app_int_sts
is
asserted, the Hard IP generates an Assert_INT<n> message TLP.
Related Information
• Interrupts for Endpoints on page 5-39
• Interrupts for Root Ports on page 5-40
PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel
interface to speed simulation; however, you cannot use the PIPE interface in actual hardware.
• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.
• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants
can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
Related Information
PIPE Interface Signals on page 5-64
Transaction Layer
The Transaction Layer is located between the Application Layer and the Data Link Layer. It generates and
receives Transaction Layer Packets. The following illustrates the Transaction Layer. The Transaction
Layer includes three sub-blocks: the TX datapath, Configuration Space, and RX datapath.
Tracing a transaction through the RX datapath includes the following steps:
1. The Transaction Layer receives a TLP from the Data Link Layer.
2. The Configuration Space determines whether the TLP is well formed and directs the packet based on
traffic class (TC).
3. TLPs are stored in a specific part of the RX buffer depending on the type of transaction (posted, non-
posted, and completion).
4. The TLP FIFO block stores the address of the buffered TLP.
5. The receive reordering block reorders the queue of TLPs as needed, fetches the address of the highest
priority TLP from the TLP FIFO block, and initiates the transfer of the TLP to the Application Layer.
6. When ECRC generation and forwarding are enabled, the Transaction Layer forwards the ECRC dword
to the Application Layer.
UG-01127_avst
2014.08.18
Interrupts 10-5
IP Core Architecture Altera Corporation
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