Altera Arria V GZ Avalon-ST - Manual (Page 16)

scripts to compile and simulate the Arria V GZ Hard IP for PCI Express IP Core. This example design
provides a simple method to perform basic testing of the Application Layer logic that interfaces to the
Hard IP for PCI Express.
For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. If
you choose the parameters specified in this chapter, you can run all of the tests included in Testbench and
Design Example chapter.
For more information about Qsys, refer to System Design with Qsys in the Quartus II Handbook. For more
information about the Qsys GUI, refer to About Qsys in Quartus II Help.
Related Information
• Understanding Simulation Log File Generation on page 2-5
• System Design with Qsys
• About Qsys
Qsys Design Flow
Copy the pcie_de_gen1_x8_ast128.qsys design example from the <install_dir>/ip/altera/altera_pcie/altera_
pcie/altera_pcie_hip_ast_ed/example_designs/<dev> to your working directory.
The following figure illustrates this Qsys system.
2-2 Qsys Design Flow
UG-01127_avst
2014.12.15
Altera Corporation Getting Started with the Arria V GZ Hard IP for PCI Express
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