Altera Arria V GZ Avalon-ST - Manual (Page 3)

Link Width
×1 ×2 ×4 ×8
PCI Express Gen3
(8.0 Gbps)
7.87 15.75 31.51 63
Refer to the AN 690: PCI Express DMA Reference Design for Stratix V Devices for more information about
calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including
the Arria V GZ Hard IP for PCI Express IP core.
Devices
Related Information
• PCI Express Base Specification 2.1 or 3.0
• AN 690: PCI Express DMA Reference Design for Stratix V Devices
• Creating a System with Qsys
Features
New features in the Quartus ® II 14.1 software release:
• Reduced Quartus II compilation warnings by 50%.
The Arria V GZ Hard IP for PCI Express supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and
Endpoints.
• Dedicated 16 KByte receive buffer.
• Optional hard reset controller for Gen2.
• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core
bitstreams to be stored separately.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
• Support for multiple packets per cycle with the 256-bit Avalon-ST interface.
• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error
reporting (AER) for high reliability applications.
• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space
and support multiple functions.
• Support for Gen3 PIPE simulation.
• Easy to use:
• Flexible configuration.
• Substantial on-chip resource savings and guaranteed timing closure.
• No license requirement.
• Example designs to get started.
1-2 Features
UG-01127_avst
2014.12.15
Altera Corporation Datasheet
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