Altera Arria V GZ Avalon-ST - Manual (Page 56)

Signal Direction Description
rx_st_valid
Output Clocks
rx_st_data
into the Application Layer. Deasserts within
2 clocks of
rx_st_ready
deassertion and reasserts within 2 clocks
of
rx_st_ready
assertion if more data is available to send.
For 256-bit data, when you turn on Enable multiple packets per
cycle, bit 0 applies to the entire bus
rx_st_data[255:0]
. Bit 1 is
not used.
rx_st_err[<n>-1:0] Output Indicates that there is an uncorrectable error correction coding
(ECC) error in the internal RX buffer. Active when ECC is
enabled. ECC is automatically enabled by the Quartus II
assembler. ECC corrects single-bit errors and detects double-bit
errors on a per byte basis.
When an uncorrectable ECC error is detected,
rx_st_err
is
asserted for at least 1 cycle while
rx_st_valid
is asserted.
For 256-bit data, when you turn on Enable multiple packets per
cycle, bit 0 applies to the entire bus
rx_st_data[255:0]
. Bit 1 is
not used.
Altera recommends resetting the Arria V GZ Hard IP for PCI
Express when an uncorrectable double-bit ECC error is detected.
Related Information
Avalon Interface Specifications.
Avalon‑ST RX Component Specific Signals
Table 5-2: Avalon-ST RX Component Specific Signals
Signal Direction Description
rx_st_mask
Input
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted at
any time. The total number of non-posted requests that can be
transferred to the Application Layer after
rx_st_mask
is asserted
is not more than 10.
5-4 Avalon‑ST RX Component Specific Signals
UG-01127_avst
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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