Altera Arria V GZ Avalon-ST - Manual (Page 169)

Note: Altera does not support the use of the LMI interface to read and write the other registers in
function0 of the Hard IP for PCI Express Configuration Space. You must create your own
function0 in your application logic.
In Configuration Space Bypass mode, the Transaction Layer disables checks for Unsupported Requests
and Unexpected Completions. The Application Layer must implement these checks. The Transaction
Layer also disables error Messages and completion generation, which the Application Layer must
implement.
Note: The following figure shows the division of error checking between the Transaction Layer of the
hard IP for PCI Express and the Application Layer. The real-time error flags assert for one
pld_clk
as the errors are detected by the Transaction Layer.
Figure 10-4: Error Handing in Configuration Space Bypass Mode
Transaction Layer of the Hard IP for PCI Express Application Layer
(Soft Logic)
Avalon-ST TX
Custom Configuration
Space
and Error Handling
Error Detect (Corrected Errs,
Malformed TLPs)
RX Buffer &
Flow Control
Avalon-ST RX
Real-Time Error Flags
(Malformed, Corrected)
LMI
Config TLPs
Errors
Completions,
Messages
Error Detect
(UR, Unexpected
Completion)
Drop Malformed
TLPs
AER Registers
UG-01127_avst
2014.08.18
Error Checking and Handling in Configuration Space Bypass Mode 10-9
IP Core Architecture Altera Corporation
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