Altera Arria V GZ Avalon-ST - Manual (Page 19)

Generating Quartus II Synthesis Files
1. On the Generate menu, select Generate HDL.
2. For Create HDL design files for synthesis, select Verilog.
You can leave the default settings for all other items.
3. Click Generate to generate files for Quartus II synthesis.
4. Click Finish when the generation completes.
Understanding the Files Generated
Table 2-2: Overview of Qsys Generation Output Files
Directory Description
<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for
PCI Express and the .qip file that lists all of the
necessary assignments and information required to
process the IP core in the Quartus II compiler.
Generally, a single .qip file is generated for each IP
core.
<testbench_dir>/<variant_name>/synthesis/submodules Includes the HDL files necessary for Quartus II
synthesis.
<testbench_dir>/<variant_name>/testbench Includes testbench subdirectories for the Aldec,
Cadence, Synopsys, and Mentor simulation tools
with the required libraries and simulation scripts.
<testbench_dir>/<variant_name>/testbench<cad_
vendor> Includes the HDL source files and scripts for the
simulation testbench.
For a more detailed listing of the directories and files the Quartus II software generates, refer to Files
Generated for Altera IP Cores in Compiling the Design in the Qsys Design Flow.
Understanding Simulation Log File Generation
Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_
monitor_<dev>_dlhip_tlp_file_log.log
in your simulation directory.
Table 2-3: Sample Simulation Log File Entries
Time TLP Type Payload
(Bytes)
TLP Header
17989 RX CfgRd0 0004 04000001_0000000F_01080008
17989 RX MRd 0000 00000000_00000000_01080000
18021 RX CfgRd0 0004 04000001_0000010F_0108002C
18053 RX CfgRd0 0004 04000001_0000030F_0108003C
UG-01127_avst
2014.12.15
Generating Quartus II Synthesis Files 2-5
Getting Started with the Arria V GZ Hard IP for PCI Express Altera Corporation
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