Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 16)

2–4 Chapter 2: Getting Started with Altera IP Cores
Qsys System Integration Tool Design Flow
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
f For more information about simulating Altera IP cores, refer to Simulating Altera
Designs in volume 3 of the Quartus II Handbook.
2.4. Qsys System Integration Tool Design Flow
You can use the Qsys system integration tool to build a system that includes your
customized IP core. You easily can add other components and quickly create a Qsys
system. Qsys automatically generates HDL files that include all of the specified
components and interconnections. In Qsys, you specify the connections you want.
The HDL files are ready to be compiled by the Quartus II software to produce output
files for programming an Altera device.
Figure 2–3 shows a high level block diagram of an example Qsys system.
f For more information about the Qsys system interconnect, refer to the Qsys
Interconnect chapter in volume 1 of the Quartus II Handbook and to the Avalon Interface
Specifications .
f
For more information about the Qsys tool and the Quartus II software, refer to the
System Design with Qsys section in volume 1 of the Quartus II Handbook and to Quartus
II Help.
2.4.1. Specify Parameters
To specify parameters for your IP core using the Qsys flow, follow these steps:
1. Open an existing Quartus II project or create a new project using the New Project
Wizard available from the File menu.
2. On the Tools menu, click Qsys.
3. On the Component Library tab, expand the Interfaces Protocols list and then the
Ethernet list. Double-click Ethernet 10G MAC to add it to your system. The
relevant parameter editor appears.
Figure 2–3. Example Qsys System
DDR3
SDRAM
Ethernet
Subsystem
Ethernet
Embedded Cntl
PCI Express
Subsystem
Qsys System
PCIe to Ethernet Bridge
PCIe
CSR
Mem
Mstr
Mem
Slave
PHY
Cntl
Mem
Mstr
CSR
DDR3
SDRAM
Controller