Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 55)

5–10 Chapter 5: 1G/10GbE MAC Design Example
1G/10GbE Testbench
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
6. Displays the MAC statistics in the transcript panel.
5.5.4.2. Backplane-KR Mode
To run backplane-KR mode in simulation, perform the following steps:
1. Open the altera_eth_10g_mac_base_kr.qsys file and edit the following
10GBASE-KR PHY instances of channels 1 and 0:
■ IP variant = Backplane-KR
■ Turn on Enable Automatic Speed Detection.
■ Turn on Enable Auto-negotiation.
■ Regenerate the Qsys system.
2. Change the default setting to backplane-KR mode.
3. Run simulation.
Upon a simulated power-on reset, the testbench performs the following operations:
1. Initializes the DUT by configuring the following options via the Avalon-MM
interface:
a. Configures the MAC. In the MAC, enables address insertion on the transmit
path and sets the transmit primary MAC address to EE-CC-88-CC-AA-EE.
b. In the TX and RX FIFO buffers (Avalon-ST Single Clock FIFO core), enables
drop on error.
c. Checks if auto-negotiation status is completed.
d. Waits for both the MAC and PHY to be ready to receive data.
2. Starts packet transmission. The testbench sends a total of eight packets:
a. Three 64-byte basic Ethernet frames
b. 1518-byte VLAN frame
c. 1518-byte basic Ethernet frame
d. 64-byte stacked VLAN frame
e. 500-byte VLAN frame
f. 1518-byte stacked VLAN frame
3. Displays the MAC statistics in the transcript panel.
5.5.5. Simulating the 1G/10GbE Testbench with the ModelSim Simulator
To use the ModelSim simulator to simulate the 1G/10GbE testbench design, perform
the following steps:
1. Copy the
<ip library>/ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_bas
e_kr
directory to your preferred project directory.
2. The design example and testbench files are set to read only. Altera recommends
that you turn off the read-only attribute of all design example and testbench files.