Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 53)

5–8 Chapter 5: 1G/10GbE MAC Design Example
1G/10GbE Testbench
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
avalon_if_params_pkg.sv
A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv
A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
eth_mac_frame.sv
A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv
A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
tb_run.tcl
A Tcl script that starts a simulation session in the ModelSim
simulation software.
tb.sv
The top-level testbench file. This file includes the customized
1G/10GbE design example, which is the device under test
(DUT), a client packet generator, and a client packet monitor
along with other logic blocks.
wave.do
A signal tracing macro script for use with the ModelSim
simulation software to display testbench signals.
Table 5–4. 1G/10GbE Testbench Files
File Name Description