Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 115)

Chapter 8: Registers 8–21
Register Initialization
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
2. PHY configuration register initialization
Altera provides various types of Ethernet PHY such as XAUI and 10GBASE-R
PHY. By default, the PHY does not need any configuration register initialization.
To ensure the transceiver PHY is operating properly, perform a hard reset to the
PHY after a power-up sequence.
//Hard Reset the Altera Transceiver PHY
Asserted the phy_mgmt_reset input at least more than 3 phy_mgmt_clk
cycles.
De-assert the phy_mgmt_reset input to release the hard reset
//Wait for the Transceiver PHY Reset Sequence to Complete
Wait the tx_ready and rx_ready outputs = 1
Or
//Check the tx_read and rx_ready status through PHY Management Interface
//XAUI/10G BASE-R PHY Base Address: 0x00040000
//reset_status byte addres: 0x108
//reset_status bit 0 – tx_ready, bit 1 – rx_ready
Wait reset_status (address = 0x00040108) = 0x3
3. Miscellaneous configuration register initialization
This is only applicable to the 10GbE MAC design example. The following
components in the design example is categorized under the miscellaneous
configuration register initialization:
■ TX and RX single-clock FIFO/dual clock FIFO
a. Setting for single-clock FIFO
//RX FIFO Base Address: 0x00010400
//TX FIFO Base Address: 0x00010600
//Enable Store and Forward Mode in RX Single-Clock FIFO
//cut_through_threshold byte address: 0x10
//Set this larger than 0 will enable Cut Through mode
cut_throught_threshold (address = 0x00010410) = 0x0
//Enable Store and Forward Mode in TX Single-Clock FIFO
//cut_through_threshold byte address: 0x10
//Set this larger than 0 will enable Cut through mode
cut_through_threshold (address = 0x00010610) = 0x0
//Enable FIFO Frame Drop On Error
//Drop on Error is NOT available in Cut Through Mode
//drop_on_error byte address: 0x14
//Set this to 0 will disable the drop on error