Altera GPIO User Manual
Altera gpio ip core user guide, Ip migration for arria v, cyclone v, and stratix v
Altera GPIO IP Core User Guide
2014.08.18
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The Altera GPIO megafunction IP core supports General Purpose I/O (GPIO) components and features.
GPIOs are I/Os used in general applications not specific to transceivers, memory-like interfaces or LVDS.
The Altera GPIO IP core features the following components:
• Double data rate input/output (DDIO)—A digital component that doubles, or halves the data-rate of a
communication channel.
• Delay chains— configure the delay chains to perform specific delay and assist in I/O timing closure.
• I/O buffers—connect the pads to the FPGA.
Note: The actual implementations and features of DDIO, delay chains, and I/O buffers vary from family
to family.
The Altera GPIO IP core is only available for Arria 10 devices. For Arria V, Cyclone V, and Stratix V
IP Migration for Arria V, Cyclone V, and Stratix V
your IP.
Related Information
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IP Migration for Arria V, Cyclone V, and Stratix V
The Altera GPIO IP core supports the IP migration flow which allows you to migrate your Arria V,
Cyclone V, and Stratix V devices IP into the Altera GPIO IP core in Arria 10 devices.
This IP migration flow configures the new IP to match the settings of the old one and allow you to
regenerate. Some IP cores only support this migration in specific modes.
If your IP core is in a mode that is not supported, you may need to run the Altera GPIO IP Parameter
Editor and configure it manually.
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Document Outline
- Altera GPIO IP Core User Guide