Altera GPIO - Manual (Page 12)

Clock Interface Signals
Signal Name Direction Description
ck
Input This clock feeds a packed register or DDIO in input and output
paths when half-rate DDIOs are not used. If the Altera GPIO IP
core is in bidirectional mode and if you turn off the Separate
Input/Output Clocks parameter, this is the unique clock for
input and output paths.
ck_fr
Input
These clocks feed full-rate and half-rate DDIO in both input and
output paths when half-rate DDIOs are used. If the Altera GPIO
IP core is in bidirectional mode and if you turn off the Separate
Input/Output Clocks parameter, the input and output paths use
these clocks.
ck_hr
ck_in
Input
These clocks feed a packed register or DDIO in the input and
output path of a bidirectional Altera GPIO when half-rate
DDIOs are not used, and separate clocks are requested by
turning on the Separate Input/Output Clocks parameter.
ck_out
ck_fr_in
Input
These clocks feed full-rate and half-rate DDIOs in the input and
output paths of a bidirectional Altera GPIO when half-rate
DDIOs are used, and separate clocks are requested by turning on
the Separate Input/Output Clocks parameter. For example,
ck_
fr_out
feeds the full-rate DDIO in the output path.
ck_fr_out
ck_hr_in
ck_hr_out
cke
Input Clock enable.
Termination Interface Signals
Signal Name Direction Description
seriesterminationcontrol
Input Input from the termination control block
(OCT) to the buffers. It sets the buffer series
impedance value.
parallelterminationcontrol
Input Input from the termination control block
(OCT) to the buffers. It sets the buffer
parallel impedance value.
Reset Interface Signals
Signal Name Direction Description
sclr
Input Synchronous clear.
aclr
Input Asynchronous clear.
aset
Input Asynchronous set.
sset
Input Synchronous set.
Shared Signals
The input, output, and OE paths share the same clear and preset signals.
The output and OE path shares the same clock signals.
12 Clock Interface Signals
ug-altera_gpio
2014.08.18
Altera Corporation Altera GPIO IP Core User Guide
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