Altera MAX 10 Clocking and PLL User Manual
Max 10 clocking and pll user guide
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Table of contents
Document Outline
- MAX 10 Clocking and PLL User Guide
- Contents
- 1. MAX 10 Clocking and PLL Overview
- 2. MAX 10 Clocking and PLL Architecture and Features
- Clock Networks Architecture and Features
- Internal Oscillator Architecture and Features
- PLLs Architecture and Features
- PLL Architecture
- PLL Features
- PLL Locations
- Clock Pin to PLL Connections
- PLL Counter to GCLK Connections
- PLL Control Signals
- Clock Feedback Modes
- PLL External Clock Output
- ADC Clock Input from PLL
- Spread-Spectrum Clocking
- PLL Programmable Parameters
- Clock Switchover
- PLL Cascading
- PLL Reconfiguration
- 3. MAX 10 Clocking and PLL Design Considerations
- 4. MAX 10 Clocking and PLL Implementation Guides
- ALTCLKCTRL IP Core
- ALTPLL IP Core
- ALTPLL_RECONFIG IP Core
- Internal Oscillator IP Core
- 5. ALTCLKCTRL IP Core References
- 6. ALTPLL IP Core References
- 7. ALTPLL_RECONFIG IP Core References
- 8. Internal Oscillator IP Core References
- A. Additonal Information for MAX 10 Clocking and PLL User Guide