Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 143)

9–24 Chapter 9: Interface Signals
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
tx_etstamp_ins_ctrl_residence_time_
calc_format
Input 1
Format of timestamp to be used for residence time
calculation.
0: 96-bits (96-bits egress timestamp - 96-bits
ingress timestamp).
1: 64-bits (64-bits egress timestamp - 64-bits
ingress timestamp).
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_checksum_zero Input 1
Assert this signal to set the checksum field of
UDP/IPv4 to zero.
Required offset location of checksum field.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_checksum_correc
t
Input 1
Assert this signal to correct UDP/IPv6 packet
checksum, by updating the checksum correction,
which is specified by checksum correction offset.
Required offset location of checksum correction.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_offset_timestam
p []
Input 16
The location of the timestamp field, relative to the
first byte of the packet.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_offset_correcti
on_field [] Input 16
The location of the correction field, relative to the
first byte of the packet.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_offset_checksum
_field [] Input 16
The location of the checksum field, relative to the
first byte of the packet.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_offset_checksum
_correction [] Input 16
The location of the checksum correction field,
relative to the first byte of the packet.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
Table 9–12. IEEE 1588v2 TX Insert Control Timestamp Interface Signals (Part 2 of 2)
Signal Direction Width Description