Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
Page 34
3–16
Chapter 3: 10GbE MAC Design Examples
10GbE Design Example Compilation and Verification in Hardware
10-Gbps Ethernet MAC MegaCore Function User Guide
February 2014
Altera Corporation
4. Load the pin assignments and I/O standards for the development board:
■
For the 10GbE MAC with XAUI PHY design example, type the following
command:
source setup_SIVGX230C2ES.tcl
r
This command assigns the XAUI serial interface to the pins that are connected
to the HSMC Port A of the Stratix IV GX development board.
■
For the 10GbE MAC with 10BASE-R design example, type the following
command:
source setup_EP4S100G2F40I1.tcl
r
This command assigns the 10GBASE-R serial interface to the pins that are
connected to the SMA connectors (J38 to J41) of the Stratix IV GT development
board.
f
For more information about the development boards, refer to the respective
reference manuals:
or
5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_r.qsys or
altera_eth_10g_mac_xaui.qsys
.
6. For the 10GbE MAC with XAUI PHY design example, the default setting of the
PHY is Hard XAUI. Follow these steps if you want to set the PHY to Soft XAUI:
a. Double-click the XAUI PHY module to open the parameter editor.
b. On the General Options tab, select Soft XAUI for XAUI Interface Type.
7. Click Save on the File menu.
8. On the Generation tab, turn on Create Synthesis RTL Files.
9. Click Generate to generate the system.
10. Click Start Compilation on the Processing menu to compile the design example.
11. Upon a successful compilation, click Programmer on the Tools menu to program
the device.
f
For more information about device programming, refer to
volume 3 of the Quartus II Handbook.
1
If you are not using the Stratix IV GX FPGA development board or the Transceiver
Signal Integrity development board, Stratix IV GT Edition, modify setup_proj.tcl and
setup_SIVGX230C2ES.tcl
or setup_EP4S100G2F40I1.tcl to suit your hardware.