Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 29)

Chapter 3: 10GbE MAC Design Examples 3–11
10GbE Testbenches
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
3.6.4. 10GbE Testbench Simulation Flow
Upon a simulated power-on reset, each testbench performs the following operations:
1. Initializes the DUT by configuring the following options via the Avalon-MM
interface:
a. In the MAC, enables address insertion on the transmit path and sets the
transmit primary MAC address to EE-CC-88-CC-AA-EE.
b. In the TX and RX FIFO (Avalon-ST Single Clock FIFO core), enables drop on
error.
2. Starts packet transmission. The testbench sends a total of eight packets:
a. 64-byte basic Ethernet frame
b. Pause frame
c. 1518-byte VLAN frame
d. 1518-byte basic Ethernet frame
e. 64-byte stacked VLAN frame
f. 500-byte VLAN frame
g. Pause frame
h. 1518-byte stacked VLAN frame
3. Ends the transmission and displays the MAC statistics in the transcript pane.
3.6.5. Simulating the 10GbE Testbench with the ModelSim Simulator
To use the ModelSim simulator to simulate the testbench design, follow these steps:
1. Copy the respective design example directory to your preferred project directory:
altera_eth_10g_mac_xaui or altera_eth_10g_mac_base_r from
<ip library>/ethernet/altera_eth_10g_design_example.
2. The design example and testbench files are set to read only. Altera recommends
that you turn off the read-only attribute of all design example and testbench files.
3. Launch the Quartus II software and open the top.v file from the project directory.
4. Open the Quartus II Tcl Console window by pointing to Utility Windows on the
View menu and then selecting Tcl Console. In the Quartus II Tcl Console window,
type the following command to set up the project environment:
source setup_proj.tcl
r
5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_r.qsys or
altera_eth_10g_mac_xaui.qsys in the File menu.
6. For the 10GbE MAC with XAUI design example, the default setting of the XAUI
PHY is Hard XAUI. Follow these steps if you want to set the PHY to Soft XAUI:
a. Double-click the XAUI PHY module to open the parameter editor.
b. On the General Options tab, select Soft XAUI for XAUI Interface Type.
7. On the Generation tab, select Verilog simulation model.