Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 25)

Chapter 3: 10GbE MAC Design Examples 3–7
Creating a New 10GbE Design
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
3. Open the Quartus II Tcl Console window by pointing to Utility Windows on the
View menu and then selecting Tcl Console. In the Quartus II Tcl Console window,
type the following command to set up the project environment:
source setup_proj.tcl
r
4. Load the pin assignments and I/O standards for the development board:
■ For the 10GbE MAC with XAUI PHY design example, type the following
command:
source setup_SIVGX230C2ES.tcl
r
This command assigns the XAUI serial interface to the pins that are connected
to the HSMC Port A of the Stratix IV GX development board.
■ For the 10GbE MAC with 10GBASE-R design example, type the following
command:
source setup_EP4S100G2F40I1.tcl
r
This command assigns the 10GBASE-R serial interface to the pins that are
connected to the SMA connectors (J38 to J41) of the Stratix IV GT development
board.
f For more information about the development boards, refer to the respective
reference manuals:
Stratix IV GX Development Kit Reference Manual or
Transceiver Signal Integrity Development kit, Stratix IV GT Edition Reference
Manual
.
5. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_r.qsys
or altera_eth_10g_mac_xaui.qsys file. For design targeting the Stratix V device
family, use the altera_eth_10g_mac_base_r_sv.qsys or
altera_eth_10g_mac_xaui_sv.qsys
file.
1 By default, the design example targets the Stratix IV device family. To
change the target device family, click on the Project Settings tab and select
the desired device from the Device family list.
6. Turn off the additional module under the Use column if your design does not
require them. This action disconnects the module from the 10GbE system.
7. Double-click eth_10g_design_example_0 to launch the parameter editor.
8. Specify the required parameters in the parameter editor. For detailed explanations
of these parameters, refer to “10GbE Design Example Parameter Settings” on
page 3–8 .
9. Click Finish.
10. On the Generation tab, select either a Verilog HDL or a VHDL simulation model
and make sure that the Create HDL design files for synthesis option is turned on.
11. Click Generate to generate the simulation and synthesis files.