Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 58)

Chapter 5: 1G/10GbE MAC Design Example 5–13
1G/10GbE Design Example Compilation
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
5.6. 1G/10GbE Design Example Compilation
You can use the Quartus II software to compile the 1G/10GbE design example and
program the targeted Altera device after a successful compilation.
5.6.1. Compiling the 1G/10GbE Design
Perform the following steps to compile the design and program the device:
1. Copy the
<ip library>/altera_eth_10g_design_example/altera_eth_10g_mac_base_kr
directory to your preferred project directory.
2. Launch the Quartus II software and open altera_eth_10g_mac_base_kr_top.v
from the project directory.
3. Open the Quartus II Tcl Console window by pointing to Utility Windows on the
View menu then clicking Tcl Console. In the Quartus II Tcl Console window, type
the following command to set up the project environment and load pin
assignments and I/O standard for the development kit:
source setup_proj.tcl
r
f For more information about the development kit, refer to Signal Integrity
Development Kit, Stratix V GX Edition User Guide .
4. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_kr.qsys.
5. Click Save on the File menu.
6. On the Generation tab, turn on Create Synthesis RTL Files.
7. Click Generate to generate the system.
8. Click Start Compilation on the Processing menu to compile the design example.
9. Upon a successful compilation, click Programmer on the Tools menu to program
the device.
10. Launch the MegaWizard Plug-in Manager. Select Edit an existing custom
megafunction variation and regenerate reconfig.v from the reconfig folder.
1 If you want to share the PLL clock, connect the pll_powerdown signal from the reset
controller to the pll_powerdown signal from different channels of the Backplane
Ethernet 10GBASE-KR PHY IP.
For example, the pll_powerdown signal from reset controller 0 connects to the
pll_powerdown
signal from channel 0 and channel 1 of the Backplane Ethernet
10GBASE-KR PHY IP.
For more information about device programming, refer to Quartus II Programmer in
volume 3 of the Quartus II Handbook.