Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 142)

Chapter 9: Interface Signals 9–23
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
Table 9–12 describes the TX insert control timestamp interface signals for the IEEE
1588v2 feature.
Table 9–12. IEEE 1588v2 TX Insert Control Timestamp Interface Signals (Part 1 of 2)
Signal Direction Width Description
tx_etstamp_ins_ctrl_timestamp_inser
t
Input 1
Assert this signal to insert egress timestamp into
the associated frame.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_timestamp_forma
t
Input 1
Timestamp format of the frame, which the
timestamp to be inserted.
0: 1588v2 format (48-bits second field + 32-bits
nanosecond field + 16-bits correction field for
fractional nanosecond)
Required offset location of timestamp and
correction field.
1: 1588v1 format (32-bits second field + 32-bits
nanosecond field)
Required offset location of timestamp.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_residence_time_
update
Input 1
Assert this signal to add residence time (egress
timestamp –ingress timestamp) into correction
field of PTP frame.
Required offset location of correction field.
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_ctrl_ingress_timesta
mp_96b [] Input 96
96-bit format of ingress timestamp.
(48 bits second + 32 bits nanosecond + 16 bits
fractional nanosecond).
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).
tx_etstamp_ins_
ctrl_ingress_timestamp_64b [] Input 64
64-bit format of ingress timestamp.
(48-bits nanosecond + 16-bits fractional
nanosecond).
Assert this signal in the same clock cycle as the
start of packet (avalon_st_tx_startofpacket
is asserted).