Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 51)

5–6 Chapter 5: 1G/10GbE MAC Design Example
Creating a New 1G/10GbE Design
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
5.4. Creating a New 1G/10GbE Design
You can use the Quartus II software to create a new 1G/10GbE design. Altera
provides a Qsys design example file that you can customize to facilitate the
development of your 1G/10GbE design.
To create the design, perform the following steps:
1. Launch the Quartus II software and open the altera_eth_10g_mac_base_kr_top.v
file from the project directory.
2. Open the Quartus II Tcl Console window by pointing to Utility Windows on the
View menu and then selecting Tcl Console. In the Quartus II Tcl Console window,
type the following command to set up the project environment and load the
necessary pins assignment for Stratix V GX signal integrity development kit
board:
source setup_proj.tcl
r
f
For more information about the development kit, refer to Signal Integrity
Development Kit, Stratix V GX Edition User Guide .
3. Launch Qsys from the Tools menu and open the
altera_eth_10g_mac_base_kr.qsys file.
1 At this point you can edit the settings to suit your design using the
parameter editor.
4. Click Finish.
5. On the Generation tab, select either a Verilog HDL or VHDL simulation model
and make sure that the Create HDL design files for synthesis option is turned on.
6. Click Generate to generate the simulation and synthesis files.
7. Launch the MegaWizard Plug-in Manager from the Tools menu. Select Edit an
existing custom megafunction variation and regenerate reconfig.v from the
reconfig folder.
8. Click Finish.
5.5. 1G/10GbE Testbench
Altera provides testbench for you to verify the 1G/10GbE design example. The
following sections describe the testbench, its components, and use.
5.5.1. 1G/10GbE Testbench
The testbench operates in loopback mode. Figure 5–4 shows the flow of the packets in
the design example.